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| ICS542 Clock Divider Description The ICS542 is a cost effective way to produce a high quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz, and produces a divide by 2, 4, 6, 8, 12, or 16 of the input clock. There are two outputs on the chip, one being a low-skew divide by two of the other. So, for instance, if a 100 MHz clock is used, the ICS542 can produce low skew 50 MHz and 25 MHz clocks, or low skew 25 MHz and 12.5 MHz clocks. The chip has an all-chip power down mode that stops the outputs low, and an OE pin that tri-states the outputs. The ICS542 is a member of the ICS ClockBlocksTM family of clock building blocks. See the ICS541 and ICS543 for other clock dividers, and the ICS501, 502, 511, 512 and 525 for clock multipliers. Features * Packaged as 8 pin SOIC * ICS' lowest cost clock divider * Low skew (500ps) outputs. One is / 2 of other. * Easy to use with other generators and buffers * Input clock frequency up to 156 MHz * Output clock duty cycle of 45/55 * Power Down turns off chip * Output Enable * Advanced, low power CMOS process * Operating voltages of 3.0 to 5.5 V Block Diagram VDD GND 2 S1, S0 Divider and Selection Circuitry Input Clock /2 Output Buffer CLK Output Buffer CLK/2 OE (both outputs) 1 Revision 050400 Printed 11/14/00 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA*95126* (408) 295-9800tel * www.icst.com MDS 542 B ICS542 Clock Divider Pin Assignment ICLK VDD GND S0 1 2 3 4 8 7 6 5 CLK CLK/2 OE S1 Clock Decoding Table S1 0 0 1 1 S0 0 1 0 1 CLK CLK/2 Power Down All Input/6 Input/12 Input/8 Input/16 Input/2 Input/4 0 = connect directly to ground. 1 = connect directly to VDD. 8 pin SOIC Pin Descriptions Number 1 2 3 4 5 6 7 8 Name ICLK VDD GND S0 S1 OE CLK/2 CLK Type CI P P I I I O O Description Clock input. Connect to +3.3V or +5V. Connect to ground. Select 0 for output clock. Connect to GND or VDD. Internal pull-up. Select 1 for output clock. Connect to GND or VDD. Internal pull-up. Output Enable. Tri-states both output clocks when low. Internal pull-up. Clock output per Table above. Low skew divide by two of pin 8 clock. Clock output per Table above. Key: CI = clock input, I = input, O = output, P = power supply connection External Components The ICS542 requires a 0.01 F decoupling capacitor to be connected between VDD and GND. It must be connected close to the ICS542 to minimize lead inductance. No external power supply filtering is required for this device. A 33 series terminating resistor can be used next to each output pin. If a 3.3 V input clock is applied to the ICLK pin, with the ICS542 at 5 V, the clock must be AC coupled. 2 Revision 050400 Printed 11/14/00 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA*95126* (408) 295-9800tel * www.icst.com MDS 542 B ICS542 Clock Divider Electrical Specifications Parameter Conditions Minimum Typical ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device) Supply Voltage, VDD Referenced to GND Inputs Referenced to GND -0.5 Clock Output Referenced to GND -0.5 Ambient Operating Temperature 0 Soldering Temperature Max of 10 seconds Storage temperature -65 DC CHARACTERISTICS (VDD = 3.3V unless otherwise noted) Operating Voltage, VDD 3 Input High Voltage, VIH, ICLK only ICLK (Pin 1) (VDD/2)+1 VDD/2 Input Low Voltage, VIL, ICLK only ICLK (Pin 1) VDD/2 Input High Voltage, VIH S0, S1, OE 2 Input Low Voltage, VIL S0, S1, OE Output High Voltage, VOH, CMOS levels IOH=-4mA VDD-0.4 Output High Voltage, VOH IOH=-12mA 2.4 Output Low Voltage, VOL IOL=4mA IDD Operating Supply Current, 100 MHz input No Load, 5.0V, 11 sel 11 IDD Operating Supply Current, 100 MHz input No Load, 3.3V, 11 sel 7 Short Circuit Current Each Output 40 Input Capacitance, S1, S0, OE Pins 4, 5, 6 4 AC CHARACTERISTICS (VDD = 3.3V unless otherwise noted) Input Frequency, clock input at VDD = 5V 0 Input Frequency, clock input at VDD = 3.3V 0 Skew of output clocks rising edges at VDD/2 Output Clock Rise Time 0.8 to 2.0V 1 Output Clock Fall Time 2.0 to 0.8V 1 Output Clock Duty Cycle at VDD/2 45 49 to 51 Maximum 7 VDD+0.5 VDD+0.5 70 260 150 5.5 (VDD/2)-1 0.8 Units V V V C C C V V V V V V V V mA mA mA pF MHz MHz ps ns ns % 0.4 156 156 500 55 3 Revision 050400 Printed 11/14/00 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA*95126* (408) 295-9800tel * www.icst.com MDS 542 B ICS542 Clock Divider Package Outline and Package Dimensions 8 pin SOIC Symbol A Inches Min Max 0.0532 0.0688 0.0040 0.0098 0.0130 0.0200 0.0075 0.0098 0.1890 0.1968 0.1497 0.1574 .050 BSC 0.2284 0.2440 0.0099 0.0195 0.0160 0.0500 Millimeters Min Max 1.35 1.75 0.10 0.24 0.33 0.51 0.19 0.24 4.80 5.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.41 1.27 E INDEX AREA H A1 B C 1 2 D A1 e C h x 45 D E e H h L A L B Ordering Information Part/Order Number ICS542M ICS542MT Marking ICS542M ICS542M Package 8 pin SOIC 8 pin SOIC on tape and reel Temperature 0 to 70 C 0 to 70 C While the information presented herein has been checked for both accuracy and reliability, ICS/MicroClock assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS/MicroClock. ICS/MicroClock reserves the right to change any circuitry or specifications without notice. ICS/MicroClock does not authorize or warrant any ICS/MicroClock product for use in life support devices or critical medical instruments. ClockBlocks is a trademark of ICS 4 Revision 050400 Printed 11/14/00 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA*95126* (408) 295-9800tel * www.icst.com MDS 542 B |
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